Day 10: Noise margins, and why CMOS burns almost only switching power
Reading the VTC for robustness
Real signals are noisy. Digital logic survives because each gate cleans up its input: anything comfortably below a threshold is treated as 0, anything comfortably above as 1, and the gate outputs a clean rail. Noise margins quantify 'comfortably'. They come from four voltages on the VTC, found where its slope is −1 (the unity-gain points).
- VOH / VOL — the output high and low voltages the gate actually produces (near Vdd and 0 for CMOS)
- VIH / VIL — the input voltages above/below which the gate reliably reads 1 / 0
- NMH = VOH − VIH — high-level noise margin
- NML = VIL − VOL — low-level noise margin
The larger NMH and NML, the more noise a wire can pick up before a driven gate misreads it. Because CMOS drives rail-to-rail (VOH ≈ Vdd, VOL ≈ 0) and has a steep transition, its noise margins are excellent — roughly Vdd/2 each in a symmetric inverter — another reason it dominates.
Why CMOS burns power almost only when it switches
Three currents exist. Static current in steady state is tiny (one transistor is off — only Stage −1 leakage remains). Dynamic current flows when the output charges or discharges its load capacitance on a transition. A brief short-circuit current also flows during the transition, while the input is near Vm and *both* transistors conduct at once. Add it up and the power bill is dominated by activity — how often nodes toggle — not by simply being powered on.
A tap that only spends water when you move the handle
An old NMOS/TTL gate is like a tap with a slow constant drip even when 'closed' (resistive pull-up → static power). A CMOS gate is like a tap that only releases water while you're actively turning the handle (charging the load) and a tiny splash as it passes the midpoint (short-circuit). Leave it still and it costs almost nothing.
Key terms
- VOH / VOL
- The high/low output voltages a gate drives (near Vdd / near 0 in CMOS).
- VIH / VIL
- Input thresholds above/below which the gate reliably interprets 1 / 0; the VTC unity-gain points.
- Noise margin (NMH, NML)
- How much noise an input can tolerate before misreading: NMH = VOH − VIH, NML = VIL − VOL.
- Short-circuit current
- Brief current through both transistors while the input passes near Vm during a transition.
- Dynamic current
- Current that charges/discharges the load capacitance on each output transition.
Before moving on, you should be able to
A CMOS gate has VOH = 4.9 V, VIH = 3.1 V, VIL = 1.9 V, VOL = 0.1 V. What is its high-level noise margin NMH?
