Day 12: RC delay, fan-out, and an intro to logical effort
How fast is a gate?
Model a conducting transistor as a switch in series with an on-resistance `Ron`, and every node as a capacitance `C` (gate, wire, and junction caps). A gate switches by driving current through Ron to charge or discharge C — a first-order RC circuit. The propagation delay is proportional to the time constant: tpd ≈ 0.69 · Ron · C. Faster means lower Ron (wider/stronger transistors) or lower C (less load).
Fan-out
Fan-out is how many gate inputs a single output drives. Each driven input adds its gate capacitance to C, so a gate driving four others is slower than one driving one. This is why big nets get buffered (a chain of increasing-strength inverters) and why a designer thinks about *drive strength* vs *load* constantly.
Propagation delay grows roughly linearly with fan-out as each load adds capacitance.
Logical effort (an intro)
Logical effort is a tidy way to compare gates: normalized delay d = g·h + p. g is the logical effort (how much worse than an inverter a gate is at driving load — a NAND's g > 1), h is the electrical effort (fan-out = load ÷ input cap), and p is parasitic delay (self-load). You'll only use it at intro level now; the point is the mental model — *delay = gate complexity × load + overhead* — which is exactly how Stage 5 timing tools think.
This RC model returns as cell timing
When Stage 5 has you read a standard cell's .lib timing arc, its delay is tabulated against input transition and output load capacitance — the very Ron/C story from this page, characterized precisely by the foundry. Learn the intuition here and the STA tables read like old friends.
Key terms
- On-resistance Ron
- The effective resistance of a conducting transistor; lower for wider (higher W/L) devices.
- Load capacitance C
- Total capacitance a node must charge: driven gate inputs + wire + self.
- RC delay
- tpd ≈ 0.69·Ron·C — propagation delay set by charging a capacitance through a resistance.
- Fan-out
- Number of gate inputs an output drives; more fan-out → more load capacitance → more delay.
- Logical effort
- A delay model d = g·h + p separating gate type (g), load (h), and self-load (p).
- Drive strength
- A gate's ability to source/sink current, set by transistor width; stronger gates charge loads faster.
Before moving on, you should be able to
Two identical gates drive the same signal, but gate A drives 2 loads and gate B drives 6 loads. Which is slower, and why?
