Day 21: Hazards and glitches in combinational logic
When correct logic still glitches
Your Boolean equations assume gates are instant. They aren't — each has a propagation delay. When an input change reaches the output through two paths of different delay, the output can briefly show the wrong value before settling: a glitch. A static-1 hazard dips momentarily to 0 when it should stay 1; a static-0 hazard blips to 1; a dynamic hazard bounces several times during a single intended transition.
F = A*B + A'*C , hold B=1, C=1, change A from 1 -> 0
term A*B : was 1 (A=1,B=1) -> becomes 0 quickly
term A'*C : was 0 -> becomes 1 but AFTER the inverter delay on A'
For a brief window BOTH terms are 0 -> F glitches to 0
(before A'*C catches up and restores F=1)
Fix: add the redundant CONSENSUS term B*C -> F = A*B + A'*C + B*C
now B*C holds F=1 through the transition.Why synchronous design tolerates glitches
In a clocked (synchronous) design you only sample combinational outputs at the clock edge — and you size the clock period so everything has *settled* by then. Glitches during the cycle are irrelevant; only the final, stable value is captured. That is the core reason the whole industry designs synchronously, and the mindset you carry into every RTL module in Stage 2.
Key terms
- Glitch
- A brief, unintended output pulse caused by unequal path delays converging at a gate.
- Static-1 / static-0 hazard
- An output that should stay 1 (or 0) but momentarily flips due to timing skew between terms.
- Dynamic hazard
- Multiple unintended transitions during a single intended output change.
- Consensus term
- A redundant product term added to a cover to bridge a hazard and keep the output steady.
- Synchronous sampling
- Capturing signals only at clock edges, after they have settled — which makes combinational glitches harmless.
Before moving on, you should be able to
In a purely synchronous design, why are combinational glitches usually not a functional problem?
