Day 23: Sequential logic II: registers and shift registers
From one flip-flop to useful storage
Put n D flip-flops side by side, all on the same clock, and you have an n-bit register — the storage element behind every CPU register (ChipX has 32 of them) and pipeline stage. Wire the flip-flops in a chain — each one's Q feeding the next one's D — and you get a shift register, which moves its contents one position every clock edge.
Shift registers convert between serial and parallel: a SIPO (serial-in, parallel-out) collects a bit stream into a word; a PISO (parallel-in, serial-out) sends a word out one bit at a time. Add a parallel load and you can snapshot a value, then shift it out. That serial↔parallel conversion is the core of nearly every communication peripheral.
A UART is a shift register at heart
ChipX's UART (Stage 2) transmits a byte by parallel-loading it into a shift register and clocking it out one bit per baud interval (a PISO); the receiver shifts incoming bits in (a SIPO) and reassembles the byte. When you build that peripheral, remember it's this humble chain of flip-flops with framing bits bolted on.
Key terms
- Register
- n D flip-flops sharing a clock, storing an n-bit word — the basic CPU/pipeline storage element.
- Shift register
- Flip-flops chained Q→D so data shifts one position per clock.
- SIPO / PISO
- Serial-in-parallel-out / parallel-in-serial-out — the two serial↔parallel conversion directions.
- Parallel load
- Loading all flip-flops with an input word in one clock, bypassing the shift path.
Before moving on, you should be able to
To send a parallel byte out over a single serial wire, which shift-register configuration do you use?
