Day 27: Timing basics: propagation delay, setup/hold, clock skew

The single inequality on this page — clock ≥ clock-to-Q + logic + setup — is the one you'll spend Stage 5 closing. Learn it cold now.

Why timing is everything

A synchronous circuit works only if data launched from one flip-flop arrives and settles at the next before the capturing clock edge. Three delays govern this: clock-to-Q (tcq, how long after the edge a flip-flop's output is valid), propagation delay (tpd, the combinational path between flip-flops), and setup time (tsu, how long data must be stable *before* the edge). There's also hold time (th), how long data must stay stable *after* the edge.

The register-to-register timing constraints

SETUP (max-delay) constraint — sets the fastest clock:
   T_clk  >=  tcq + tpd(max) + tsu
   slack  =  T_clk - (tcq + tpd_max + tsu)   ;  must be >= 0

HOLD (min-delay) constraint — independent of clock period:
   tcq + tpd(min)  >=  th
   (data must not race through and change the input too soon)

Clock skew (clock arrives late at the capture FF by 'skew'):
   helps setup:  T_clk + skew >= tcq + tpd_max + tsu
   hurts hold:   tcq + tpd_min >= th + skew

You are learning STA, three stages early

That setup inequality *is* static timing analysis setup slack (Stage 5) — same terms, same arithmetic, just done by a tool across millions of paths instead of by you on one. And the hold constraint's independence from clock period is why 'hold violations are scarier' (you can't fix them by slowing the clock). Memorize both now; Stage 5 becomes revision.

Key terms

Propagation delay (tpd): Time for a signal to travel through combinational logic between flip-flops.
Clock-to-Q (tcq): Delay from the clock edge to a flip-flop's output becoming valid.
Setup time (tsu): How long data must be stable before the clock edge to be captured correctly.
Hold time (th): How long data must remain stable after the clock edge; violations are independent of clock period.
Clock skew: Difference in clock arrival time between two flip-flops; helps setup but hurts hold.
Slack: Margin between required and actual timing; must be ≥ 0 for the path to work.

Before moving on, you should be able to

Write T_clk ≥ tcq + tpd_max + tsu and define every term
Explain the hold constraint and why it is independent of clock period
Explain how clock skew helps setup but hurts hold
Compute setup slack for a path given the numbers

A path has tcq = 0.2 ns, tpd(max) = 1.5 ns, tsu = 0.1 ns. What is the minimum clock period for correct operation (zero skew)?

Day 27: Timing basics: propagation delay, setup/hold, clock skew

Why timing is everything

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