Day 39: The single-cycle datapath: the ALU
The single-cycle datapath begins: the ALU
A single-cycle CPU executes one full instruction per clock — every instruction's whole journey (fetch → decode → execute → memory → writeback) happens within one long cycle. It's slow but the clearest way to see the datapath. Its compute core is the ALU: given two operands and an operation select, it produces a result and status flags (notably zero, used by branches).
For RV32I the ALU needs: ADD/SUB (your Stage-0 adder, with SUB via two's-complement negation), bitwise AND/OR/XOR, shifts (SLL/SRL/SRA), and comparisons (SLT/SLTU — set-less-than, signed and unsigned). A small ALU control decodes the instruction's funct3/funct7 into the operation select.
Stage 0 pays off
The adder trade-off you studied on Day 19 is now real: this ALU's ADD/SUB is on the CPU's critical path, so whether you use ripple-carry or lookahead directly affects ChipX's clock. And SUB reusing the adder via two's complement (Day 15) is why one adder serves both — the ISA was designed for it.
Key terms
- Single-cycle CPU
- A design executing one complete instruction per (long) clock cycle.
- ALU
- Arithmetic-logic unit — computes add/sub, logic, shifts, and comparisons with status flags.
- Zero flag
- An ALU output asserted when the result is zero; used to resolve branches (beq/bne).
- SLT / SLTU
- Set-less-than (signed) and its unsigned form — comparison instructions producing 0/1.
- ALU control
- Small logic decoding funct3/funct7 (and opcode) into the ALU operation select.
Before moving on, you should be able to
How does the ALU produce the input a branch (beq) needs to decide whether to jump?
