Day 42: Draw the whole single-cycle CPU from memory
The complete single-cycle datapath
Assemble the pieces into one picture: PC → instruction memory → decode (register file + imm-gen) → ALU → data memory → writeback mux, with the control unit steering the muxes and the next-PC logic choosing pc+4, a branch target, or a jump target. Being able to draw this from memory — every mux, every control signal — is the Day-42 milestone.
Trace a few instructions through it out loud: an add (registers → ALU → writeback), a lw (ALU computes address → memory → writeback), a sw (ALU address, rs2 → memory, no writeback), a beq (ALU compares, zero flag → next-PC mux). If every instruction's path is obvious, you're ready to pipeline it.
This drawing is a real deliverable
The roadmap ships the paper pipeline design into docs/stage1/. Start it as this single-cycle drawing; Days 43–47 evolve it into the 5-stage pipeline with every forwarding and stall path annotated. Hand-drawn, scanned, and committed — craft is a deliverable, and a hiring manager can read your understanding straight off it.
Ship for Day 42
In the single-cycle datapath, what does the writeback (MemToReg) mux choose between?
