Day 48: Memory hierarchy: SRAM vs DRAM, and the cache idea
The memory hierarchy
Fast memory is small and expensive; big memory is slow. The memory hierarchy stacks them: registers (fastest), then SRAM caches (fast, 6 transistors/bit, no refresh), then DRAM main memory (dense, 1 transistor + capacitor/bit, needs refresh), then storage. The trick that makes it work is locality: programs reuse recent data (temporal) and nearby data (spatial), so a small fast cache captures most accesses.
A cache holds recently/nearby-used blocks of memory close to the CPU. A hit is served fast; a miss falls through to slower memory and brings the block up. Because of locality, hit rates are high (often >90%), so average access time stays close to the fast level despite most *bytes* living in slow memory. ChipX's optional I-cache (Stage 2 stretch) is a direct-mapped instance of this idea.
Desk, drawer, warehouse
Registers are the papers in your hand; the cache is your desk; DRAM is the filing cabinet; storage is the offsite warehouse. You keep what you're using on the desk because walking to the warehouse for every page would be unbearable — and it works precisely because you tend to reuse the same few pages (locality).
Key terms
- SRAM
- Static RAM — fast, 6T bitcell, holds state without refresh; used for caches.
- DRAM
- Dynamic RAM — dense 1T1C bitcell needing periodic refresh; used for main memory.
- Temporal / spatial locality
- Reuse of recently accessed data / access to nearby addresses; the basis for caching.
- Cache hit / miss
- Data found in (hit) or absent from (miss) the cache; misses fetch from slower memory.
- Memory hierarchy
- The speed/size tiers from registers down to storage that together approximate fast-and-big.
Before moving on, you should be able to
Why does a small SRAM cache dramatically speed up a system whose data mostly lives in slow DRAM?
