Day 50: Virtual memory, the TLB, and DMA
Virtual memory, the TLB, and DMA
Virtual memory gives each process its own address space, mapped to physical memory by page tables (fixed-size pages, typically 4 KB). It enables isolation, larger-than-RAM address spaces (paging to disk), and relocation. Every access must translate a virtual address to physical — too slow to do via the page table each time, so a TLB (translation lookaside buffer) caches recent translations, making the common case a single fast lookup.
DMA (direct memory access) lets peripherals move blocks of data to/from memory *without* the CPU copying each word — the CPU sets up the transfer and gets an interrupt when it's done, freeing it to compute. ChipX itself has no MMU/virtual memory (frozen scope — it's a microcontroller-class core), but these concepts are core interview material and explain the systems your firmware runs within.
Scope discipline
ChipX deliberately has no MMU, no virtual memory — that's v2.0 territory, and adding it would violate the frozen spec (failure mode #7). You still learn it cold because BARC/ISRO and industry loops ask it, and because knowing what you *chose to leave out* — and why — is itself a strong interview answer.
Key terms
- Virtual memory
- Per-process address spaces mapped to physical memory via page tables.
- Page / page table
- A fixed-size memory block and the structure mapping virtual pages to physical frames.
- TLB
- A cache of recent virtual→physical translations that avoids walking the page table each access.
- DMA
- Peripheral-driven block memory transfer that offloads copying from the CPU.
- MMU
- Memory-management unit performing translation and protection — absent in ChipX by design.
Before moving on, you should be able to
What problem does the TLB solve?
