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S−1 · Sand to Silicon
35 min

Day 6: The MOSFET: threshold, triode, saturation, and the square-law

The MOSFET is the transistor ChipX is (eventually) made of. Threshold, triode, saturation, and the square-law are the vocabulary of every digital interview.

From MOS capacitor to MOSFET

Start with a MOS capacitor: a gate metal, a thin insulating oxide, and the semiconductor beneath. Sweeping the gate voltage moves the silicon surface through three states — accumulation (majority carriers pile up), depletion (they're pushed away), and finally inversion, where enough *minority* carriers gather at the surface to form a conducting channel of the opposite type. The gate voltage at which inversion forms is the threshold voltage `V_T`.

Four terminals, and turning on

An NMOS transistor adds a source and drain (n+ regions) either side of a p-type body, with the gate over the channel between them. When Vgs > V_T, an inversion channel of electrons connects source to drain; the drain-to-source voltage Vds then pushes current Id through it. Below V_T the channel is absent and the device is (nearly) off — that switch is the entire basis of digital logic.

Triode vs saturation

With the channel on, two regimes appear. In triode (a.k.a. linear/ohmic), Vds < Vgs − V_T: the channel is continuous and the device behaves like a voltage-controlled resistor. Raise Vds past Vgs − V_T and the channel pinches off near the drain — you enter saturation, where Id becomes nearly independent of Vds and depends on the overdrive (Vgs − V_T) squared. That's the famous square-law.

The square-law drain current (long-channel NMOS)
Let  k = mu * Cox * (W/L)        ; process x geometry
     Vov = Vgs - V_T               ; overdrive voltage

Cutoff      (Vgs < V_T):     Id = 0
Triode      (Vds < Vov):     Id = k * [ Vov*Vds - Vds^2 / 2 ]
Saturation  (Vds >= Vov):    Id = (k/2) * Vov^2          ; ~flat in Vds

Boundary: Vds = Vov = Vgs - V_T  (channel just pinches off at the drain)

Digital uses the switch; timing needs the curve

In CMOS logic a transistor mostly toggles between cutoff and triode — off, or a low-resistance path. But the overdrive (Vgs − V_T) and the square-law set how *fast* it can dump charge onto a load, which is exactly the RC/drive-strength intuition behind gate delay in Stage 0 and cell timing in Stage 5. Know the switch for logic, the curve for speed.

Key terms

Threshold voltage V_T
The gate voltage at which an inversion channel forms and the MOSFET turns on.
Inversion
The MOS surface state where minority carriers form a conducting channel of the opposite type to the body.
Overdrive voltage
Vov = Vgs − V_T; the "how far on" measure that drives current in the square-law.
Triode / linear region
Vds < Vov: continuous channel, device acts as a voltage-controlled resistor.
Saturation region
Vds ≥ Vov: channel pinched off at the drain, Id ≈ constant in Vds, ∝ Vov².
k = μCox(W/L)
The transconductance parameter — process (μCox) times geometry (W/L) — scaling the drain current.
Aspect ratio W/L
Channel width over length; the designer’s main knob for a transistor’s drive strength.

Before moving on, you should be able to

An NMOS has V_T = 0.5 V. It is biased at Vgs = 1.5 V, Vds = 0.4 V. Which region is it in?

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