Day 71: Peripheral: SPI master — all four modes
Peripheral: SPI master — all four modes
SPI is a synchronous, full-duplex, master-driven bus: SCLK (clock), MOSI (master-out), MISO (master-in), and a per-slave CS (chip select). The subtlety is the four modes set by CPOL (clock idle polarity) and CPHA (clock phase — sample on leading or trailing edge). Master and slave must agree, or you read garbage; getting CPOL/CPHA right is the whole game.
Mode CPOL CPHA idle SCLK data sampled on
0 0 0 low leading (rising) edge
1 0 1 low trailing (falling) edge
2 1 0 high leading (falling) edge
3 1 1 high trailing (rising) edge
Master shifts data out on the opposite edge from where it samples,
so the slave sees stable data at its sample edge.Full-duplex by design
SPI shifts one bit out (MOSI) and one bit in (MISO) on every clock — it's inherently full-duplex, a single shift-register exchange between master and slave. That's why a 'read' still requires clocking out dummy bytes. ChipX's SPI master will drive flash and sensors; making CPOL/CPHA configurable via its register interface is what makes it reusable.
Key terms
- SPI
- Synchronous full-duplex bus: SCLK, MOSI, MISO, and chip-select, master-driven.
- CPOL
- Clock polarity — whether SCLK idles low (0) or high (1).
- CPHA
- Clock phase — whether data is sampled on the leading or trailing clock edge.
- Chip select (CS)
- Per-slave enable line, asserted (usually active-low) for the duration of a transfer.
Ship for Day 71
What do the SPI parameters CPOL and CPHA together determine?
