Skip to main content...
S2 · Verilog RTL Design
25 min

Day 74: Peripheral: the 32-bit timer

A timer is the CPU's sense of time — periodic interrupts, delays, PWM. It's a counter with compare logic and a register interface.

Peripheral: the 32-bit timer

A timer/counter gives software a sense of time. At its core: a 32-bit counter that increments each clock (or each prescaled tick), a compare/reload value, and an interrupt when the counter reaches it. From this you get periodic interrupts (RTOS tick), one-shot delays, and — with an output toggle — PWM. It's your Stage-0 counter plus compare logic plus a register interface.

A 32-bit down-counter timer with reload and interrupt
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin count <= 0; irq <= 0; end
    else if (enable) begin
        if (count == 0) begin
            count <= reload;         // auto-reload for periodic mode
            irq   <= 1'b1;           // fire interrupt
        end else begin
            count <= count - 1'b1;
            if (irq_clear) irq <= 1'b0;
        end
    end
end
// a prescaler (divide clk by N) sets the tick period; reload sets the count

This drives your RTOS tick later

The periodic interrupt from this timer is exactly what a scheduler needs for time-slicing — you'll use it in Stage D's FreeRTOS work, and in Stage 4 firmware for delays. A prescaler (divide the clock before counting) lets one 32-bit timer span microseconds to minutes. Small module, huge reuse.

Ship for Day 74

What is the purpose of a timer’s prescaler?

We use cookies

We use cookies to enhance your browsing experience, serve personalized content, and analyze our traffic. By clicking "Accept All", you consent to our use of cookies. Learn more

    Day 74: Peripheral: the 32-bit timer | RBTechIconX