Day 76: Wrapping every peripheral behind AXI-Lite

Wrapping every peripheral behind the same AXI-Lite interface is what turns a pile of modules into an addressable system.

Wrapping every peripheral behind AXI-Lite

Now standardize: give UART, SPI, I²C, GPIO, and the timer each an AXI-Lite slave wrapper exposing their control/status registers at a fixed address range. The CPU then configures any peripheral by writing memory-mapped registers — no special per-peripheral bus. A consistent register-map convention (offset 0 = control, 4 = status, 8 = data, …) makes firmware and documentation uniform.

One interface, uniform firmware

Because every peripheral speaks AXI-Lite with a consistent register layout, your Stage-4 firmware drivers all look alike: write(base + CTRL, ...), read(base + STATUS). This uniformity is the point of a standard bus — and it's what lets you add a peripheral later (Stage D accelerators) without touching the CPU or fabric.

Ship for Day 76

Give each peripheral an AXI-Lite slave wrapper
Adopt a consistent register-map convention across peripherals
Assign each a non-overlapping address range
Verify CPU-style reads/writes reach the right peripheral

What is the main benefit of wrapping every peripheral behind the same AXI-Lite register interface?

Day 76: Wrapping every peripheral behind AXI-Lite

Wrapping every peripheral behind AXI-Lite

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