Day 78: The 2-FF synchronizer and the CDC rules you can recite
The 2-FF synchronizer and CDC rules
The workhorse is the 2-flip-flop synchronizer: two flip-flops in the destination clock domain, the first absorbing metastability, the second delivering a resolved bit (Stage 0). Around it sits a set of CDC rules — from the Cummings papers — that you should be able to recite and point to in your own design.
module sync2 (
input clk_dst, rst_n,
input d_async, // from another clock domain
output q_sync
);
reg s1, s2;
always @(posedge clk_dst or negedge rst_n)
if (!rst_n) {s2, s1} <= 2'b00;
else {s2, s1} <= {s1, d_async};
assign q_sync = s2; // metastability-resolved
endmodule- Synchronize every single-bit control signal crossing domains with a 2-FF synchronizer
- Never synchronize a multi-bit bus bit-by-bit — use gray code or a handshake
- Never let a synchronized signal fan out to two synchronizers (they may disagree)
- Pass multi-bit data via an async FIFO (gray pointers) or a req/ack handshake with stable data
- Keep synchronizer flip-flops physically close (a Stage-6 constraint) to maximize resolution time
Recite them in the interview
'Explain every Cummings CDC rule and where your design applies it' is a named Stage-2 exit criterion. Being able to *point at your async FIFO and say why the pointers are gray-coded*, or *at your control synchronizer and say why it's 2-FF* is exactly the concrete, applied knowledge that lands DV and RTL offers.
Before moving on, you should be able to
Why must you avoid letting one asynchronous signal feed two separate synchronizers?
