Day 8: Leakage, short-channel effects & why scaling changed everything
The transistor that never fully turns off
Below threshold, a MOSFET's current doesn't snap to zero — it falls off *exponentially* with Vgs. This subthreshold conduction is the same exp(V/Vt) physics you measured in the diode, and it means every 'off' transistor still leaks a little. The steepness is the subthreshold swing: how many millivolts of Vgs you must drop to cut current by 10×. Physics floors it at ~60 mV/decade at room temperature — a limit that shaped the entire low-power era.
Where leakage comes from
- Subthreshold leakage — the exponential off-state channel current (dominant, and worse as V_T drops)
- Gate leakage — electrons tunneling through an oxide only a few atoms thick
- Junction leakage — reverse-biased source/drain junctions passing a small current
Add these across *billions* of transistors and leakage becomes static power — power burned while the chip does nothing. That's why P = α·C·V²·f + P_leak: the first term is the useful switching you met in Stage 0, the second is the tax you pay just for being powered on.
Short-channel effects
As channel length L shrinks, the tidy long-channel model breaks. DIBL (drain-induced barrier lowering): a high Vds reaches in and lowers the source barrier, so V_T *droops* with drain voltage. Velocity saturation: carriers hit a top speed in high fields, so current grows more slowly than the square-law predicts. V_T roll-off: threshold drifts with tiny length variations. Together these are why SPICE models at advanced nodes are vastly more complex than Day 6's clean equations.
Why scaling changed everything
For decades, Dennard scaling promised that shrinking transistors let you drop voltage too, keeping *power density* constant — smaller, faster, and cooler every generation, for free. Around the mid-2000s it broke: V_T and supply voltage couldn't keep falling without leakage exploding, so power density stopped improving. The industry's answers — multi-core instead of ever-higher clocks, power gating, multi-Vt cell libraries, and new device shapes (FinFET, then GAA) — are the direct reason Stage 5's low-power design topics exist.
The cheat sheet you ship today gets revised twice
docs/stage_minus1/devices.md is not a one-and-done note. In Stage 5 you'll revise it when *multi-Vt* cells give leakage a design meaning; in Stage 7 you'll revise it again for *aging* (BTI/HCI). Device physics is a thread that runs the whole roadmap, not a box ticked in week one.
Ship: docs/stage_minus1/devices.md
Write the one-page device cheat sheet: the MOSFET I–V regions and square-law, V_T / body effect / channel-length modulation, and the leakage + short-channel + scaling story. This is the Stage −1 capstone deliverable — and the source you'll reread before every device-physics interview question.
Key terms
- Subthreshold conduction
- Exponential drain current below V_T; the main source of static leakage.
- Subthreshold swing
- mV of Vgs needed to change Id by 10×; floored near 60 mV/decade at room temperature.
- DIBL
- Drain-induced barrier lowering — high Vds lowers the source barrier, dropping V_T in short channels.
- Velocity saturation
- Carriers reaching a maximum drift velocity in high fields, so current grows sub-quadratically.
- Gate leakage
- Quantum tunneling of carriers through an ultra-thin gate oxide.
- Dennard scaling
- The (now-ended) rule that shrinking devices with voltage kept power density constant.
- Multi-Vt
- Mixing high-/standard-/low-threshold cells to trade leakage against speed — a Stage 5 low-power lever.
Stage −1 exit criteria
Why does static (leakage) power become a first-class problem as process nodes shrink?
