Day 83: The direct-mapped I-cache controller (stretch)
The direct-mapped I-cache controller (stretch)
As a stretch goal, build a small direct-mapped instruction cache for ChipX, turning Stage-1 cache theory (Day 49) into RTL. Each fetch address splits into tag/index/offset; the index selects a line; the stored tag is compared; on a hit the instruction comes from the cache in one cycle; on a miss the controller stalls the fetch, fetches the block from memory, fills the line, and updates the tag/valid bits.
wire [TAGW-1:0] tag = addr[31:31-TAGW+1];
wire [IDXW-1:0] index = addr[OFFW+IDXW-1:OFFW];
wire [OFFW-1:0] offset= addr[OFFW-1:0];
wire hit = valid[index] && (tags[index] == tag);
// on hit : instr = data_line[index][offset]; single cycle
// on miss : stall fetch; run a small FSM to refill the line from memory,
// then set valid[index]=1, tags[index]=tag, and retryTheory becomes a state machine
The miss handler is a small FSM — LOOKUP → (hit? done : REFILL) → UPDATE → retry — exactly the FSM discipline from Stage 0 applied to the cache mechanics from Stage 1. It's optional for ChipX, but building one is a strong portfolio and interview asset ('here's a real cache I wrote'), and it makes AMAT concrete.
Ship (stretch) for Day 83
In a direct-mapped cache, what determines a hit?
