Day 1: Wafer fabrication: sand to a patterned wafer

One product, from sand to silicon

Everything in this roadmap — every module, testbench, script, and FPGA demo — contributes to one chip: the ChipX SoC, an RV32I processor you'll carry from a paper design all the way to a real GDSII layout. Stage −1 is the physical ground floor: how a raw silicon wafer becomes a patterned canvas of billions of transistors. You will never *fabricate* ChipX yourself, but knowing this process is what makes later phrases like *standard cell*, *metal layer*, *parasitic*, and *DRC* mean something concrete instead of magic.

The single most useful mental model for a fab: it is a photographic printing process, repeated in layers. A pattern on a mask is projected onto a light-sensitive coating, developed, and etched into the wafer — then the whole loop runs again for the next layer, dozens of times, until a flat slice of silicon holds a full 3-D structure of transistors and wires.

From sand to a monocrystalline ingot

Silicon starts as purified polysilicon and is grown into a single crystal by the Czochralski process: a seed crystal is dipped into molten silicon and slowly pulled upward while rotating, growing a cylindrical boule that is one continuous crystal lattice. The boule is sliced into thin wafers and polished mirror-flat. It has to be a *single* crystal — grain boundaries in a polycrystalline slice would scatter carriers and ruin transistor behavior.

Photolithography: the expose–develop–etch loop

Each layer is patterned the same way. Grow or deposit a film (e.g. thermally grow SiO₂), spin on a light-sensitive photoresist, then expose it to UV through a photomask/reticle carrying that layer's pattern. Develop washes away the exposed (or unexposed) resist, leaving a stencil; etch removes the film where it is unprotected; finally strip the remaining resist. Repeat for every mask layer in the design.

Doping: diffusion vs ion implantation

To make a region n-type or p-type, dopant atoms are introduced into the silicon. Diffusion drives them in thermally; ion implantation — dominant today — fires accelerated dopant ions into the wafer, giving precise control of *dose* (how many) and *depth* (how deep), followed by a thermal anneal to repair the lattice and activate the dopants. These doped regions become the sources, drains, and wells of your transistors.

FEOL, BEOL, CMP, and the metal stack

Fabrication splits into two halves. FEOL (front-end-of-line) builds the transistors themselves in and just above the silicon. BEOL (back-end-of-line) wires them together with many stacked metal layers (M1, M2, … up to a dozen+), separated by insulating dielectric and connected vertically by vias. After each metal layer, CMP (chemical-mechanical planarization) polishes the surface flat so the next layer can be patterned. In the tiny wires of the BEOL, *interconnect delay* — not the transistors — often dominates timing at modern nodes.