Day 2: Packaging, assembly & yield: dicing to flip-chip, and the die-per-wafer math
After the wafer: dicing, packaging, and the yield question
A finished wafer is still just a disc of hundreds of identical dies. Wafer-level probe test flags the dead ones, then the wafer is diced into individual dies, each packaged so it can connect to a board, and final-tested before shipping. Much of this assembly and test work is done by specialist OSAT firms (Outsourced Semiconductor Assembly and Test) rather than the fab itself.
Wire bond vs flip-chip
Two ways to connect a die's pads to the package. Wire bonding runs fine gold or copper wires from pads on the die's top surface to the package leadframe — cheap and ubiquitous, but the wires add inductance and limit I/O count. Flip-chip flips the die face-down and joins it via a grid of solder bumps directly onto the package substrate — far more I/O, shorter electrical paths, and better power/thermal delivery, at higher cost.
Substrates, chiplets, and 2.5D/3D (vocabulary)
The package substrate fans the die's connections out to the board's larger pitch. Advanced packaging goes further: chiplets split a big design into smaller dies (each with better yield) reconnected in one package; fan-out packaging skips the substrate; 2.5D places multiple dies on a silicon interposer (e.g. TSMC's CoWoS, used for GPU + HBM); 3D stacks dies vertically (e.g. Intel's Foveros). You only need these as vocabulary now — but interviewers love hearing them used correctly.
Yield: the economics of the whole industry
Not every die works. Defect density D0 (defects per cm²) captures how dirty a process is. The classic Poisson yield model says a die of area A survives with probability Y = exp(−A·D0) — one random killer defect anywhere on the die kills it. Separately, gross die per wafer (how many dies physically fit) falls as die area rises, with extra loss at the round wafer's edge.
import math
wafer_d_mm = 300.0 # 300 mm wafer
die_mm = (2.0, 2.0) # a small ChipX-class die: 2 mm x 2 mm
A_cm2 = (die_mm[0] * die_mm[1]) / 100.0 # die area in cm^2 = 0.04
# gross die per wafer (a common first-order estimate with edge loss)
r = wafer_d_mm / 2.0
A_die_mm2 = die_mm[0] * die_mm[1]
gross = (math.pi * r**2) / A_die_mm2 - (math.pi * wafer_d_mm) / math.sqrt(2 * A_die_mm2)
for D0 in (0.1, 0.5, 1.0): # defects per cm^2
Y = math.exp(-A_cm2 * D0)
print(f"D0={D0}/cm^2 yield={Y:.3f} good dies ~= {gross * Y:.0f}")
# D0=0.1 yield=0.996 good dies ~= 17337
# D0=0.5 yield=0.980 good dies ~= 17064
# D0=1.0 yield=0.961 good dies ~= 16733Poisson yield Y = exp(−A·D0) collapses as die area grows — the reason big dies are expensive.
Big dies are punished twice
Double the die area and you get *fewer* gross dies per wafer and a *lower* yield on each — so cost per good die rises much faster than area. This is exactly why the ChipX spec is frozen small (RV32I, 16 KB SRAM) and why the industry moved to chiplets: many small, high-yield dies beat one giant low-yield die.
Key terms
- OSAT
- Outsourced Semiconductor Assembly and Test — firms (ASE, Amkor) that dice, package, and test dies for fabless/foundry customers.
- Wire bond
- Fine wires from the die's top pads to the package leadframe; cheap, higher inductance, limited I/O.
- Flip-chip
- Die mounted face-down on solder bumps; many more I/O and better electrical/thermal paths, higher cost.
- Interposer
- A silicon (or organic) layer carrying multiple dies side-by-side in 2.5D packaging, e.g. CoWoS.
- Defect density (D0)
- Killer defects per unit area (defects/cm²) — the headline number for how clean a process is.
- Poisson yield
- Y = exp(−A·D0): probability a die of area A has zero killer defects.
- Gross die per wafer
- How many dies physically fit on a wafer, before yield — falls as die area rises, with edge loss.
- KGD
- Known-good die — a die that has passed test and is fit to package or integrate.
Before moving on, you should be able to
A die has area 1 cm² and the process has defect density D0 = 0.5 /cm². Using the Poisson model, roughly what fraction of dies are defect-free?
