Day 18: Combinational design I: mux, demux, decoder, encoder
The combinational building blocks
Above the gate level sit reusable combinational blocks. A multiplexer (mux) selects one of N inputs onto its output using log2(N) select lines. A demultiplexer routes one input to one of N outputs. A decoder turns an n-bit code into one-hot activation of 2ⁿ lines; an encoder does the reverse, and a priority encoder resolves multiple active inputs by rank.
2:1 mux: Y = (S' * A) + (S * B)
S=0 -> Y=A , S=1 -> Y=B
4:1 mux from three 2:1 muxes (two select bits S1 S0):
level 0: m0 = mux(S0, A, B) m1 = mux(S0, C, D)
level 1: Y = mux(S1, m0, m1)Muxes are everywhere in a CPU
In Stage 1 you'll draw ChipX's datapath and it will be *full* of muxes: choosing the ALU's second operand (register vs immediate), selecting the next PC (sequential vs branch target), and — critically — the forwarding muxes that pick a value from a later pipeline stage to resolve a data hazard. Every one is exactly the block on this page.
Key terms
- Multiplexer (mux)
- Selects 1 of N data inputs onto the output using log2(N) select lines.
- Demultiplexer
- Routes one input to one of N outputs chosen by select lines.
- Decoder
- Converts an n-bit input into one-hot activation of one of 2ⁿ outputs.
- Encoder
- Converts a one-hot (or active) input set into an n-bit code; the inverse of a decoder.
- Priority encoder
- An encoder that outputs the index of the highest-priority active input when several are active.
Before moving on, you should be able to
A 2:1 mux has Y = S′·A + S·B. If the mux instead has 8 data inputs, how many select lines does it need?
