Day 34: What an ISA is; RV32I and the register model
The machine ChipX will become
Before writing a line of RTL, you design the *machine*. An ISA (instruction-set architecture) is the contract between software and hardware: the registers, instructions, and memory model a program can rely on, independent of how the hardware implements them. RISC-V is an open ISA; its base integer subset RV32I is deliberately tiny — a few dozen instructions — which is exactly why it's the right target for a first CPU.
RV32I's state is minimal: 32 general-purpose registers (x0–x31, each 32 bits), a program counter (pc), and byte-addressable memory. x0 is hard-wired to zero — reading it always gives 0, writing it is discarded — a trick that makes many instructions fall out for free (a mov is addi rd, rs, 0, a nop is addi x0, x0, 0).
Why RISC, and why open
RISC (reduced instruction set) means simple, fixed-length, load/store instructions — easy to pipeline (Day 43) and to build. RISC-V being open means no license, a real toolchain, and a spec you read as a primary source. That combination is why it went from a Berkeley teaching ISA to shipping in real silicon — and why your ChipX résumé line reads as industrially relevant.
Key terms
- ISA
- Instruction-set architecture — the hardware/software contract: registers, instructions, memory model.
- RV32I
- The 32-bit base integer RISC-V subset; a few dozen instructions and 32 registers.
- Register file
- The 32 general-purpose registers x0–x31; x0 is hard-wired to zero.
- Program counter (pc)
- The register holding the address of the current/next instruction.
- Load/store architecture
- Only load and store touch memory; all arithmetic works on registers.
Before moving on, you should be able to
In RV32I, what is special about register x0?
