Day 33: Ship Stage 0: simulator + measured VTC + “how a flip-flop works” note
Ship day: closing out CMOS + digital logic
By today, no digital circuit should feel like magic — everything reduces first to transistors, then to gates you can draw, build, and time. Consolidate the stage into its committed deliverables and write the note that forces you to articulate the whole chain from silicon to flip-flop.
The Stage 0 ship list
- Measured CMOS inverter VTC (CD4007) with Vm and noise margins annotated (Day 14)
- Gate-level logic simulator in Python — README, unit tests, waveform screenshot (Days 30–31)
- Three breadboard builds: the counter+7-seg, the traffic-light FSM, and the combination lock (Days 25, 32)
- A 2-page "How a flip-flop actually works" note — in your own words, all the way down to the transistors
Ship: docs/stage0/flip_flop_explained.md
Write the flip-flop note: from the cross-coupled-NAND SR latch, to the transparent D latch, to the master-slave edge-triggered flip-flop — and why edge-triggering is what makes synchronous timing (Day 27) work. Assemble docs/stage0/ with the VTC, simulator link, and build photos, and commit. Stage 0 is shipped.
What you can now do that most freshers can't
Sketch a CMOS inverter VTC and mark noise margins; write P = αCV²f from memory; minimize any ≤5-variable K-map in under 10 minutes; design a Mealy sequence detector cold and verify it in your own simulator; explain metastability with a timing diagram. That's a Stage-0 interview checkpoint most self-taught candidates can't clear — and you measured half of it on a breadboard.
Next up (Stage 1) you stop building gates and start building the machine: the RISC-V ISA, a single-cycle then pipelined datapath on paper, and an instruction-set simulator that becomes ChipX's golden reference model. Everything from this stage — muxes, adders, registers, FSMs, timing — is the vocabulary that datapath is written in.
Stage 0 exit criteria
Which single fact best explains why CMOS logic replaced older families like NMOS and TTL for digital design?
