S2 · Verilog RTL Design
25 min
Day 66: Building block: LFSRs and pseudo-random generation
An LFSR makes pseudo-random bits from a handful of flip-flops — used for test patterns, scramblers, and your BER tester in Stage D.
Building block: LFSRs
A linear-feedback shift register (LFSR) is a shift register whose input bit is the XOR of selected tap positions. With well-chosen taps (a primitive polynomial), an n-bit LFSR cycles through all 2ⁿ−1 non-zero states — a cheap pseudo-random sequence generator. Uses: test-pattern generation (BIST, Stage 5), data scrambling, and the AWGN-noise/BER tester in Stage D.
An 8-bit maximal-length LFSR (taps 8,6,5,4)
module lfsr8 (
input clk, rst_n,
output reg [7:0] state
);
wire feedback = state[7] ^ state[5] ^ state[4] ^ state[3];
always @(posedge clk or negedge rst_n)
if (!rst_n) state <= 8'hFF; // any non-zero seed
else state <= {state[6:0], feedback};
endmodule
// cycles through 255 states before repeating; state 0 is a lock-up (avoid)The all-zeros lock-up
An XOR-feedback LFSR has a dead state: all zeros feeds back zero forever. Seed it non-zero (or use XNOR feedback, whose dead state is all-ones). Small detail, real bug — and a nice interview point about why the sequence length is 2ⁿ−1, not 2ⁿ.
Ship for Day 66
Why does a maximal-length n-bit XOR LFSR cycle through 2^n − 1 states rather than 2^n?
