Day 91: Integrating the AXI4-Lite fabric
Integrating the AXI4-Lite fabric
Connect the CPU to its peripherals through the AXI4-Lite interconnect fabric: one master (the CPU's memory interface) and N slaves (UART, SPI, I²C, GPIO, timer, memories). The fabric decodes the address to route each access to the right slave and returns its response. With a single master, arbitration is trivial — the fabric is mostly address decode + response muxing.
A memory map is a contract
Define ChipX's memory map explicitly — which address range is ROM, SRAM, and each peripheral — and document it. Firmware (Stage 4) and the linker script depend on it; the fabric's decoder implements it. A clear, committed memory map in docs/ is both an engineering necessity and a portfolio signal of system-level thinking.
Progress for Day 91
With a single AXI master (the CPU), what is the fabric’s primary job?
