Day 92: Wiring peripherals into chipx_top
Wiring peripherals into chipx_top
Assemble the full SoC in `chipx_top`: instantiate the core, the AXI fabric, boot ROM and SRAM, and every peripheral, wiring their AXI slave ports to the fabric and their interrupt lines back to the core. This top-level integration is where system-level issues appear — address-map overlaps, mis-wired interrupts, reset distribution — that no single module test would reveal.
module chipx_top (
input clk, rst_n,
input rx, output tx, // UART pins
inout [15:0] gpio, // GPIO pins
// SPI, I2C pins ...
);
core_sc_or_pipe u_core (.clk(clk), .rst_n(rst_n), .m_axi(cpu_axi), .irq(irq));
axi_fabric u_fab (.m(cpu_axi), .s({rom, ram, uart_s, spi_s, i2c_s, gpio_s, tmr_s}));
uart u_uart (.axi(uart_s), .rx(rx), .tx(tx), .irq(irq_uart));
timer u_tmr (.axi(tmr_s), .irq(irq_timer));
gpio u_gpio(.axi(gpio_s), .pins(gpio), .irq(irq_gpio));
// ... spi, i2c, memories ...
assign irq = irq_uart | irq_timer | irq_gpio; // (or a proper controller)
endmoduleIntegration bugs are their own species
Every sub-block passed its self-check, yet the assembled system can still fail — an overlapping address range, a swapped interrupt line, a reset that doesn't reach one block. That's precisely why Stage 3 (verification) exists and is the biggest stage: unit correctness ≠ system correctness. A quick smoke test (blink an LED, echo a UART byte) at the top level catches the grossest wiring errors now.
Progress for Day 92
Why can chipx_top fail even when every sub-module passed its own self-checking testbench?
