Day 96: Why verification is the largest stage (and the largest job market)
Why this is the biggest stage
Design Verification (DV) is the largest hiring segment in VLSI — the DV teams at Qualcomm, NVIDIA, Samsung, MediaTek, and Marvell dwarf their design teams. A verification-strong portfolio literally doubles the roles you can interview for. That's why this stage is 55 days, the roadmap's center of gravity, and the one you must not skip or fake (failure mode #4).
The core mindset shift: finding your design's bugs is a discipline, not an afterthought. You'll build stimulus that explores the state space, checkers that catch wrong behavior automatically, and coverage that *measures what you tested*. 'It passed my directed tests' (where Stage 2 ended) is where real verification begins — because directed tests only prove the cases you already thought of.
The canonical DV question
'Verify a FIFO — what's your plan?' is the interview opener you'll answer dozens of times. The structure of a good answer *is* this stage: enumerate features, design stimulus (directed + constrained-random), build checkers (scoreboard + assertions), and define coverage (functional + code) with a closure target. Learn to give that four-part answer fluently.
Key terms
- Design Verification (DV)
- The discipline of proving a design is correct; the largest VLSI hiring segment.
- Directed vs constrained-random
- Hand-written specific tests vs randomized stimulus shaped by constraints to explore broadly.
- Scoreboard
- A checker comparing DUT behavior against an independent reference model.
- Functional coverage
- A measure of which interesting scenarios your tests actually exercised.
Before moving on, you should be able to
Why is passing a set of directed tests not sufficient verification of a design?
