Day 95: Ship Stage 2 (RTL READY): core passes riscv-tests + full peripheral set
Ship Stage 2 (RTL READY)
This is the Day-95 RTL READY milestone. ChipX now has a pipelined RV32I core passing rv32ui in Verilator with zero -Wall warnings, a full peripheral set (UART, SPI, I²C, GPIO, timer) behind AXI-Lite, sync and async FIFOs, and 50+ committed RTL modules. You are now genuinely interviewable for RTL-design roles — with a real core to point at.
Stage 2 exit criteria
- ChipX passes rv32ui in Verilator with zero warnings at -Wall
- Compute async-FIFO depth for given rates and burst on paper
- Whiteboard a UART receiver cold, including baud-rate tolerance
- Explain every Cummings CDC rule and where your design applies it
What Stage 3 does with this
You've *shown* ChipX works via directed tests and the ISS diff — but that's not the same as *proving* it. Stage 3 (the roadmap's biggest, 55 days) builds an industry-shape UVM environment, an AXI VIP, an ISA scoreboard against this very ISS, SVA, and coverage closure — because DV is half the industry's jobs, and 'it passed my tests' is where most self-taught engineers stop and real verification begins.
Stage 2 shipping checklist
ChipX passes all your directed rv32ui tests and the ISS diff. Why is Stage 3 (verification) still the roadmap’s largest stage?
