Day 93: Bring-up: running rv32ui on the pipelined core
Bring-up: rv32ui on the pipelined core
Run the full rv32ui suite on the *pipelined* core in Verilator, comparing architectural state against the ISS after each retired instruction. Where the single-cycle core (Day 86) validated the datapath, this validates the *pipeline* — forwarding, stalls, and flushes — under real instruction sequences with real hazards. When it passes, ChipX's central claim ('pipelined RV32I passing riscv-tests') is true.
Failures now are hazard bugs
Because the single-cycle core already passed, any new failure on the pipeline is almost certainly a hazard bug: a missing forward, a mishandled load-use, a botched flush, or an x0 edge case. The ISS comparison points at the first diverging instruction; the hazard it involves tells you which control path to inspect. This is the payoff of building single-cycle first.
Ship for Day 93
The single-cycle core already passes rv32ui. If the pipelined core then fails a test, what is the most likely cause?
