Day 94: Closing out warnings: Verilator -Wall clean
Closing out warnings: Verilator -Wall clean
Correct isn't enough — professional RTL is also lint-clean. Run Verilator with `-Wall` and eliminate every warning: inferred latches, width mismatches (assigning a 5-bit value to a 32-bit target unintentionally), unconnected ports, implicit nets, and unused signals. Each warning is a latent bug or a readability smell; a zero-warning build is a named Stage-2 exit criterion.
verilator --lint-only -Wall chipx_top.v
# common fixes:
# WIDTH -> make bit widths match explicitly, or use sized literals
# LATCH -> assign defaults / complete case (Day 59)
# UNUSED -> remove or /* verilator lint_off UNUSED */ deliberately
# IMPLICIT-> declare every net; use `default_nettype none
# goal: verilator --lint-only -Wall -> no warnings`default_nettype none` catches typos
Add ` default_nettype none ` at the top of your files: it disables Verilog's dangerous auto-creation of one-bit wires from typos (a mistyped signal name silently becomes a new floating net). Combined with -Wall`, it turns a whole class of silent bugs into loud compile errors — a habit every serious RTL shop enforces.
Ship for Day 94
Why add `default_nettype none to your Verilog files?
